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July 2000
ML4790*
Adjustable Output, Low Ripple Boost Regulator
GENERAL DESCRIPTION
The ML4790 is a high efficiency, PFM (Pulse Frequency Modulation), boost switching regulator connected in series with an integrated LDO (Low Dropout Regulator) that incorporates "Silent SwitcherTM" technology. This technique incorporates a patented tracking scheme to minimize the voltage drop across the LDO and increase the total efficiency of the regulator beyond that which can be obtained by using a discrete external LDO regulator. The ML4790 is designed to convert single or multiple cell battery inputs to regulated output voltages for integrated circuits and is ideal for portable communications equipment that cannot tolerate the output voltage ripple normally associated with switching regulators. An integrated synchronous rectifier eliminates the need for an external Schottky diode and provides a lower forward voltage drop, resulting in higher conversion efficiency.
FEATURES
s s
Incorporates "Silent SwitcherTM" technology to deliver very low output voltage ripple (typically 5mV) Guaranteed full load start-up and operation at 1.0V input and low operating quiescent current (<100A) for extended battery life Pulse Frequency Modulation and internal synchronous rectification for high efficiency Minimum external components Low ON resistance internal switching MOSFETs Adjustable output voltage (2.5V to 5.5V)
s s s s
(* Indicates Part is End Of Life as Of July 1, 2000)
BLOCK DIAGRAM
L1
*CIN
VIN
C2 1 VL 6 5 VBOOST
VBAT 7
SHDN VOUT 4 BOOST CONTROL FEEDBACK LDO CONTROL R1 SENSE 3 R2 8 2 GND PWR GND - VOUT CFB COUT + VOUT
FROM POWER MANAGEMENT
Patent Pending *Optional
1
ML4790
PIN CONNECTION
ML4790 8-Pin SOIC (S08N)
VIN GND SENSE VOUT
1 2 3 4 8 7 6 5
PWR GND SHDN VL VBOOST
TOP VIEW
PIN DESCRIPTION
PIN NO. PIN NO.
NAME
FUNCTION
NAME
FUNCTION
1 2 3 4
VIN GND SENSE VOUT
Battery input voltage Analog signal ground Programming pin for setting the output voltage LDO linear regulator output
5 6 7
VBOOST VL SHDN
Boost regulator output for connection of an output filter capacitor Boost inductor connection Pulling this pin high shuts down the regulator, isolating the load from the input
8
PWR GND Return for the NMOS boost transistor
2
ML4790
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VBOOST ........................................................................ 7V Voltage on Any Other Pin ... GND -0.3V to VBOOST +0.3V Peak Switch Current (IPEAK) .......................................... 1A Average Switch Current (IAVG) ............................... 500mA LDO Output Current ............................................. 250mA Junction Temperature .............................................. 150C Storage Temperature Range .................... -65C to +150C Lead Temperature (Soldering 10s) .......................... +260C Thermal Resistance (JA) Plastic SOIC .................................................... 110C/W
OPERATING CONDITIONS
Temperature Range ML4790CS-X ............................................ 0C to +70C ML4790ES-X ......................................... -20C to +70C VIN Range ML4790CS-X ................................................ 1.0V to 6V ML4790ES-X ................................................. 1.1V to 6V VOUT Range .................................................. 2.5V to 5.5V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VIN = Operating Voltage Range, TA = Operating Temperature Range. (Note 1)
PARAMETER Supply VIN Current VIN = 6V SHDN = high VOUT Quiescent Current VL Quiescent Current PFM Regulator Pulse Width (TON) LDO SENSE Comparator Threshold Voltage Load Regulation See Figure 1 VIN = 1.2V, IOUT < 10mA VIN = 2.4V, IOUT < 75mA See Figure 1 VIN = 1.2V, IOUT < 10mA VIN = 2.4V, IOUT < 75mA 5 194 4.85 4.85 200 5.0 5.0 206 5.15 5.15 300 500 mV V V mV mV mVP-P 4.5 5 5.5 s VBOOST = VOUT + 0.5V 60 15 8 75 25 10 1 A A A A CONDITIONS MIN TYP. MAX UNITS
Dropout Voltage
Output Ripple Shutdown SHDN Threshold SHDN Bias Current
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
22H (Sumida CD54)
0.5 -100
0.8
1.0 100
V nA
ML4790
VIN 100F 1nF 931k 39.2k VIN GND SENSE VOUT PWR GND SHDN VL VBOOST IOUT VOUT 100F 33F
Figure 1. Application Test Circuit
3
ML4790
FUNCTIONAL DESCRIPTION
The ML4790 combines Pulse Frequency Modulation (PFM) and synchronous rectification to create a boost converter that is followed by a low dropout linear regulator (LDO). This combination creates a low output ripple boost converter that is both highly efficient and simple to use. The PFM regulator charges a single inductor for a fixed period of time and then completely discharges before another cycle begins, simplifying the design by eliminating the need for conventional current limiting circuitry. Synchronous rectification is accomplished by replacing an external Schottky diode with an on-chip PMOS device, reducing switching losses and external component count. The integrated LDO reduces the output ripple voltage to less than 5mV peak-to-peak. Integrating the LDO along with the PFM regulator allows the circuit to be optimized for very high efficiency using a patented feedback technique. It also allows the LDO to provide the maximum ripple rejection over the operating frequency range of the regulator. A block diagram of the ML4790 is shown in Figure 2. The PFM stage is comprised of Q1, Q2, A1, A2, the one shot, the flip-flop, and externals L1 and C2. The LDO stage is comprised of Q3, A3, the offset voltage control, and external components R1, R2 and COUT. Since the LDO actually controls the operation of the PFM regulator, the operation of the LDO stage will be covered first. LDO OPERATION The LDO stage operates as a linear regulator. A3 is the error amplifier, which compares the output voltage through the divider R1 and R2 to the reference, and Q3 is the pass device. When the output voltage is lower than desired, the output of A3 increases the gate drive of Q3, which reduces the voltage drop across it and brings the output back into regulation. Similarly, if the output voltage is higher than desired, A3 adjusts the gate drive of Q3 for more drop and the output is brought back into regulation.
450 400 350 300 250 200 150 100
VOS (mV)
0
10
20
30
40
50
60
70
80
90 100
IOUT (mA)
Figure 3. LDO VOS versus output current. Also included in the LDO stage is an offset voltage control. This circuit monitors the output current and adjusts the offset voltage according the general characteristic shown in Figure 3. The offset control ensures that the PFM stage provides just enough "overhead" voltage for the LDO stage to operate properly.
L1 6 5
C2 ILOAD 4 Q2 Q3 + A2 - A3 - VREF R2 + 3 R1 CFB COUT
R S
5s ONE SHOT
Q1
A1
- + +- VOS = f (ILOAD)
Figure 2. PFM Regulator and LDO Block Diagram
4
ML4790
Note, that at lower output voltages there is less voltage required at the PFM stage, and therefore less gate drive available for the pass device Q3. This results in Q3 being more resistive and unable to deliver as much output current as a ML4790 set for a higher output voltage. This characteristic is shown in Figure 4.
200 180 160 140
SHUTDOWN The SHDN pin should be held low for normal operation. Raising the voltage on SHDN above the threshold level will release the gate of Q3, which effectively becomes an open circuit. This also prevents the one shot from triggering, which keeps switching from occurring.
DESIGN CONSIDERATIONS
INDUCTOR Selecting the proper inductor for a specific application usually involves a trade-off between efficiency and maximum output current. Choosing too high a value will keep the regulator from delivering the required output current under worst case conditions. Choosing too low a value causes efficiency to suffer. It is necessary to know the maximum required output current and the input voltage range to select the proper inductor value. The maximum inductor value can be estimated using the following formula:
3.5V VOUT (V) 4.5V 5.5V
IOUT (mA)
120 100 80 60 40 20 0 2.5V
Figure 4. ML4790 IOUT MAX VIN = VOUT - 0.5V, L = 22H PFM REGULATOR OPERATION When the output of the PFM stage, VBOOST (pin 5), is at or above the dropout voltage, VOUT + VOS, the output of A1 stays low and the circuit remains idle. When VBOOST falls below the required dropout voltage, the output of A1 goes high, signaling the regulator to deliver charge to the capacitor C2. Since the output of A2 is normally high, the output of the flip-flop becomes SET. This triggers the one shot to turn Q1 on and begins charging L1 for 5s. When the one shot times out, Q1 turns off, allowing L1 to flyback and momentarily charge C2 through the body diode of Q2. But, as the source voltage of Q2 rises above the drain, the current sensing amplifier A2 drives the gate of Q2 low, causing Q2 to short out the body diode. The inductor then discharges into C2 through Q2. The output of A2 going low also serves to RESET the flip-flop in preparation for the next charging cycle. When the inductor current in Q2 falls to zero, the output of A2 goes high, releasing Q2`s gate, allowing the flip-flop to be SET again. If the voltage at VBOOST is still low, A1 will initiate another pulse. Typical inductor current and voltage waveforms are shown in Figure 5.
VIN(MIN) x TON(MIN) x LMAX = 2 x (VOUT + VOS ) x IOUT(MAX)
2
(1)
where is the efficiency, typically between 0.75 and 0.85, and VOS is the dropout voltage at IOUT(MAX) taken from Figure 3. Note that this is the value of inductance that just barely delivers the required output current under worst case conditions. A lower value may be required to cover inductor tolerance, the effect of lower peak inductor currents caused by resistive losses, and minimum dead time between pulses. Another method of determining the appropriate inductor value is to make an estimate based on the typical performance curves given in Figures 6 and 7. Figure 6 shows maximum output current as a function of input voltage for several inductor values. These are typical performance curves and leave no margin for inductance and ON-time variations. To accommodate worst case conditions, it is necessary to derate these curves by at least 10% in addition to inductor tolerance. For example, a two cell to 5.5V application requires 40mA of output current while using an inductor with 15% tolerance. The output current should be derated by 25% to 50mA to cover the combined inductor and ON-time tolerances. Assuming that 2V is the end of life voltage of a two cell input, Figure 6 shows that with a 2V input, the ML4790 delivers 52mA with a 22H inductor.
INDUCTOR CURRENT
Q(ONE SHOT)
Q1 ON Q1 & Q2 OFF
Q2 ON
Q1 ON
Q2 ON
Figure 5. PFM Inductor Current Waveforms and Timing.
5
ML4790
Figure 7 shows efficiency under the conditions used to create Figure 6. It can be seen that efficiency is mostly independent of input voltage and is closely related to inductor value. This illustrates the need to keep the inductor value as high as possible to attain peak system efficiency. As the inductor value goes down to 10H, the efficiency drops to between 70% and 75%. With 47H, the efficiency reaches approximately 90% and there is little room for improvement. At values greater than 47H, the operation of the synchronous rectifier becomes unreliable at low input voltages because the inductor current is so small that it is difficult for the control circuitry to detect as shown for the 5.5V output. After the appropriate inductor value is chosen, it is necessary to find the minimum inductor current rating required. Peak inductor current is determined from the following formula:
IL(PEAK ) =
TON(MAX) x VIN(MAX) LMIN
(2)
It is important to note that for reliable operation, make sure that IL(PEAK) does not exceed the 1A maximum switch current rating. In the two cell application previously described, a maximum input voltage of 3V would give a peak current of 880mA. When comparing various inductors, it is important to keep in mind that suppliers use different criteria to determine their ratings. Many use a conservative current level, where inductance has dropped to 90% of its normal level. In any case, it is a good idea to try inductors of various current ratings with the ML4790 to determine which inductor is the best choice. Check
200 180 160
VOUT = 5.5V
L = 22H
180 160 140
VOUT = 4.5V
L = 22H
IOUT MAX (mA)
120 100 80 60 40 20 0 1.0 2.0 3.0 VIN (V) 4.0 5.0 L = 10H
IOUT MAX (mA)
140
L = 10H 120 100 80 60 40 20 0 1.0
L = 47H
L = 47H
1.5
2.0
2.5 VIN (V)
3.0
3.5
4.0
140 120 100 80 60
VOUT = 3.5V
L = 10H L = 22H
35 30 25
IOUT MAX (mA)
VOUT = 2.5V
L = 10H
L = 22H
IOUT MAX (mA)
20 L = 47H 15 10 5 0 1.0
L = 47H 40 20 0 1.0
1.5
2.0 VIN (V)
2.5
3.0
1.2
1.4
1.6 VIN (V)
1.8
2.0
Figure 6. Output Current versus Input Voltage.
6
ML4790
efficiency and maximum output current, and if a current probe is available, look at the inductor current to see if it looks like the waveform shown in Figure 5. The DC resistance of the inductor should be kept to a minimum to reduce losses. A good rule of thumb is to allow 5 to 10m of resistance for each H of inductance. Also, be aware that the DC resistance of an inductor usually isn`t specified tightly, so an inductor with a maximum DC resistance spec of 150m may actually have 100m of resistance. Suitable inductors can be purchased from the following suppliers: Coilcraft Coiltronics Dale Sumida (708) 639-6400 (407) 241-7876 (605) 665-9301 (708) 956-0666 BOOST CAPACITOR The boost capacitor (C2) supplies current to the load during the ON-time of Q1 and will limit the ripple the LDO stage has to contend with. The ripple on C2 is influenced by three capacitor parameters: capacitance, ESL, and ESR. The contribution due to capacitance can be determined by looking at the change in the capacitor voltage required to store the energy delivered by the inductor in a single charge-discharge cycle, as given by the following formula:
C2
TON x VIN (in Farads) 2 x L x VBOOST x (VOUT - VIN)
2
2
(3)
For example, a 2.4V input, a 5V output, a 22H inductor, and an allowance of 100mV of ripple on the boost capacitor results in a minimum C2 value of 15F.
100 95 90
EFFICIENCY (%)
VOUT = 5.5V
L = 47H
100 95 90 85
L = 22H
VOUT = 4.5V
L = 47H
EFFICIENCY (%)
85 80 75 70 65 60 55 50 1.0 2.0 3.0 VIN (V) 4.0 5.0 L = 10H
80 75 70 65 60 55 50 1.0 1.5 2.0 2.5 VIN (V) 3.0 L = 10H
L = 22H
3.5
4.0
100 95 90
VOUT = 3.5V
100 95
VOUT = 2.5V
L = 47H
EFFICIENCY (%)
90 85 80 75 70 65 60 55
L = 47H
EFFICIENCY (%)
85 80 75 70 65 60 55 50 1.0 1.5 2.0 VIN (V) 2.5 3.0 L = 10H L = 22H
L = 22H
L = 10H
50 1.0
1.2
1.4
1.6 VIN (V)
1.8
2.0
Figure 7. Typical Efficiency at maximum output current as a Function of VIN.
7
ML4790
The boost capacitor`s Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL), also contribute to the ripple due to the inductor discharge current waveform. Just after the NMOS transistor turns off, the output current ramps quickly to match the peak inductor current. This fast change in current through the boost capacitor`s ESL causes a high frequency (5ns) spike that can be over 1V in magnitude. After the ESL spike settles, the boost voltage still has a ripple component equal to the inductor discharge current times the ESR. This component will have a sawtooth waveshape and can be calculated using the following formula:
ESR VBOOST (in ) IL(PEAK )
SETTING THE OUTPUT VOLTAGE The adjustable output can be set to any voltage between 2.5V and 5.5V by connecting a resistor divider to the SENSE pin as shown in the block diagram. The resistor values R1 and R2 can be calculated using the following equation:
VOUT = 0.2 x
(R1 + R2) R2
(5)
The value of R2 should be 40k or less to minimize bias current errors. R1 is then found by rearranging the equation:
(4)
For example, a 2.4V input, a 22H inductor, and an allowance of 100mV of ripple on the boost capacitor results in a maximum ESR of 200m. Therefore, a boost capacitor with a capacitance of 22F or 33F, an ESR of less than 200m, and an ESL of less than 5nH is a good choice. Tantalum capacitors which meet these requirements can be obtained from the following suppliers: AVX Sprague OUTPUT CAPACITOR The LDO stage output capacitor (C1) is required for stability and to provide a high frequency filter. An output capacitor with a capacitance of 100F, an ESR of less than 100m, and an ESL of less than 5nH is a good general purpose choice. INPUT CAPACITOR Unless the input source is a very low impedance battery, it will be necessary to decouple the input with a capacitor with a value of between 47F and 100F. This filtering prevents the input ripple from affecting the ML4790 control circuitry, and it also improves efficiency by reducing I-squared R losses during the charge and discharge cycles of the inductor. Again, a low ESR capacitor (such as tantalum) is recommended. (207) 282-5111 (207) 324-4140
V R1 = R2 x OUT - 1 0.2
(6)
It is important to note that the accuracy of these resistors directly affects the accuracy of the output voltage. The SENSE pin threshold variation is 3%, and the tolerances of R1 and R2 will add to this to determine the total output variation. Input noise may cause output ripple to become excessive due to "pulse grouping," where the charge-discharge pulses are not evenly spaced in time. In such cases it may be necessary to add a small 500pF to 1000pF ceramic feedback capacitor (CFB) from the VOUT pin to the SENSE pin.
8
ML4790
LAYOUT
Good PC board layout practices will ensure the proper operation of the ML4790. Important layout considerations include: * Use adequate ground and power traces or planes * Keep components as close as possible to the ML4790 * Use short trace lengths from the inductor to the VL pin and from the output capacitor to the VBOOST pin. * Use a single point ground for the ML4790 ground pins, and the input and output capacitors A sample PC board layout is shown in Figure 8.
Figure 8. Sample PC Board Layout.
9
ML4790
PHYSICAL DIMENSIONS inches (millimeters)
Package: S08 8-Pin SOIC
0.189 - 0.199 (4.80 - 5.06) 8
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51) SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
ORDERING INFORMATION
PART NUMBER ML4790CS ML4790ES TEMPERATURE RANGE 0C to +70C -20C to +70C PACKAGE 8-Pin SOIC (S08) (End Of Life) 8-Pin SOIC (S08) (End Of Life)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4790-01 04/28/97 Printed in U.S.A.

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